CGO-2004 Advance Program

Monday, March 22, 2004

Welcome and Keynote I

9:00am-10:00am, Monday March 22

Welcome

9:00am-9:05am

• Carole Dulong, General Chair
• Mike Smith, Program Chair

Keynote I

9:05am-10:00am

• Amitabh Srivastava
  Is Performance Research Done?
  Microsoft

Break

10:00am-10:30am

Session 1: Optimizing Memory Performance

10:30am-12:00noon

• Ispike: A Post-link Optimizer for the Intel Itanium Architecture
  Chi-Keung Luk, Robert Muth, Harish Patil, Robert Cohn, Geoff Lowney (Intel)
• Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
  Dongkeun Kim (Intel), Steve Shih-wei Liao (Intel), Perry Wang (Intel), Juan del Cuvillo (Intel), Xinmin Tian (Intel), Xiang Zou (Intel), Hong Wang (Intel), Donald Yeung (U. of Maryland College Park), Milind Gikar (Intel), John Shen (Intel)
• Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads
  Antonia Zhai, Christopher B. Colohan (CMU), J. Gregory Steffan (U. of Toronto), Todd C. Mowry (CMU)

Lunch

12:00-1:30pm

Session 2: New Frameworks

1:30-3:00pm

• VHC: Quickly Building an Optimizer for Complex Embedded Architectures
  Michael Dupre, Nathalie Drach, Olivier Temam (U. of Paris South)
• SYZYGY - A Framework for Scalable Cross-Module IPO
  Sungdo Moon, Xinliang Li, Robert Hundt, Dhruva Chakrabarti, Luis Lozano, Uma Srinivasan, Shin-Ming Liu (Hewlett-Packard)
• LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation
  Chris Lattner, Vikram Adve (U. of Illinois at Urbana-Champaign)
  

Break

3:00-3:30pm

Session 3: More Memory Performance

3:30-5:00pm

• Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems
  Kim Hazelwood (Harvard), James E. Smith (U. of Wisconsin Madison)
• Improving 64-Bit Java IPF Performance by Compressing Heap References
  Ali-Reza Adl-Tabatabai, Jay Bharadwaj, Marsha Eng, Jesse Fang, Brian T. Lewis, Brian R. Murphy, James Stichnoth (Intel), Michal Cierniak (Microsoft)
• A Dynamically Tuned Sorting Library
  Xiaoming Li, Maria Jesus Garzaran, David Padua (U. of Illinois at Urbana-Champaign)
  

Break

5:00-5:30pm

Session 4: Optimizing for Energy Efficiency

5:30-6:30pm

• Software-Controlled Operand-Gating
  Ramon Canal (Universitat Politecnica de Catalunya), Antonio Gonzalez (Universitat Politecnica de Catalunya and Intel Labs), James E. Smith (U. of Wisconsin Madison)
• Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture
  Yoav Almog, Roni Rosner, Naftali Schwartz, Ari Schmorak (Intel Labs)
  

Dinner (On your own)

Spontaneous BOF and Dessets - Special interest working groups

7:30-9:00pm

Tuesday, March 23, 2004

Session 5: Loop Scheduling

9:00-10:30am

• Probabilistic Predicate-Aware Modulo Scheduling
  Mikhail Smelyanskiy, Scott Mahlke, Edward Davidson (U. of Michigan)
• Single-Dimension Software Pipelining for Multi-Dimensional Loops
  Hongbo Rong (U. of Delaware), Zhizhong Tang (Tsinghua University), R. Govindarajan (U. of Delaware), Alban Douillet (U. of Delaware), Guang Gao (U. of Delaware)
• Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops
  Hongbo Rong, Alban Douillet, R. Govindarajan, Guang Gao (U. of Delaware)
  

Break

10:30-11:00am

Keynote II

11:00am-12:00noon

• Keith Cooper
  Evolving the Next Generation of Compilers
  Rice University

Lunch (On your own)

12:00-2:00pm

Session 6: Instruction Scheduling

2:00-3:30pm

• Exploring the Performance Potential of Itanium Processors with ILP-based Scheduling
  Sebastian Winkel (Saarland University)
• FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
  Manjunath Kudlur, Kevin Fan, Michael Chu, Rajiv Ravindran, Nathan Clark, Scott Mahlke (U. of Michigan)
• Using Dynamic Binary Translation to Fuse Dependent Instructions
  Shiliang Hu, James E. Smith (U. of Wisconsin Madison)

Break h4>

3:30-4:00pm

Session 7: Code Profiling

4:00-5:30pm

• The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators
  Youfeng Wu (Intel Labs), Mauricio Breternitz (Intel Labs), Justin Quek (U. of Illinois at Urbana-Champaign), Oma Etzion (Intel Labs), Jesse Fang (Intel Labs)
• Targeted Path Profiling: Lower Overhead Path Profiling for Staged Dynamic Optimization Systems
  Rahul Joshi (U. of Illinois at Urbana-Champaign), Michael Bond (U. of Texas at Austin), Craig Zilles (U. of Illinois at Urbana-Champaign)
• Extending Path Profiling across Loop Backedges and Procedure Boundaries
  Sriraman Tallam, Xiangyu Zhang, Rajiv Gupta (U. of Arizona)
  

Conference Dinner

6:00-8:00pm

Business meeting

9:00pm

Wedneday, March 24, 2004

Session 8: Compile-time Optimization

9:00-10:00am

• Optimizing translation out of SSA using renaming constraints
  Fabrice Rastello (ENS Lyon), Francois de Ferriere, Christophe Guillon (STMicroelectronics)
• A Compiler Scheme for Reusing Intermediate Computation Results
  Yonghua Ding, Zhiyuan Li (Purdue University)
  

Break

10:00-10:30am

Session 9: Memory Profiling and Data Layout

10:30-12:00noon

• Custom Data Layout for Memory Parallelism
  Byoungro So (IBM T.J.Watson), Mary Hall (USC-ISI), Heidi Ziegler (USC-ISI)
• Static Identification of Delinquent Loads
  Vlad-Mihai Panait (Politehnica University of Bucharest), Amit Sasturkar (Stony Brook University), Weng-Fai Wong (National University of Singapore)
• Exposing Memory Access Regularities Using Object-Relative Memory Profiling
  Qiang Wu, Artem Pyatakov, Alexey N. Spiridonov, Easwaran Raman, Douglas W. Clark, David I. August (Princeton University)
  
  
  

Closing ceremonies

12:00-12:30pm