Programme

As the use of computers proliferates, the complexity and variety of systems continues to grow. As a result, it is becoming increasingly inflexible to “hard wire” behaviours into software. Software developers can enable more control over their software configurations by exploiting Domain Specific Languages (DSLs). Such DSLs provide a systematic way to structure the underlying computational components: to coin a phrase, a DSL is a library with syntax. There is an enormous variety of DSLs for a very wide range of domains. Most DSLs are highly idiosyncratic, reflecting both the specific natures of their application domains and their designers’ own preferences. This workshop will bring together constructors of DSLs for “real world” domains; that is, DSLs intended primarily to aid in building software to solve real world problems rather than to explore the more theoretical aspects of language design and implementation. We are looking for submissions that present the motivation, design, implementation, use and evaluation of such DSLs.

ACM have accepted our application for publishing the proceedings from the workshop. Submissions will be published in the ACM Digital Library within its International Conference proceedings Series.

Adapting code initially written in a “neutral” algorithmic style to be executed in heterogeneous architectures (featuring e.g. GPGPUs, FPGAs), and later maintaining it, is a difficult and error-prone task.  It requires knowledge about the programming model of the destination architecture, about what the original code does, and about the execution environment.  The situation is even worse when the same code needs to run in different platforms or when different sections of the same application ought to run (for, e.g., time or resource optimization purposes) in different architectures.  Assistance in (and, if possible, automation of) the process of code adaptation is of course advantageous and needs knowledge and reasoning capabilities similar to those that human programmers have.  This workshop will focus on techniques and foundations to make it possible to perform source-to-source code transformations which preserve the intended semantics of the original code aiming at producing code which is better suited to be executed in different target architectures.

The increased processing capability of mobile and embedded platforms is enabling more and more ambitious machine vision applications.  Industry players are actively pushing embedded vision in the entertainment, automotive and robotics domains. Mobile vision couples high computational requirements with the heterogeneous power constrained systems. This makes it an ideal platform on which to evaluate, amongst other things, processor architectures, memory efficiency, resource scheduling, mapping, and energy efficient techniques. The ASR-MOV workshop intends to bring together system researchers to discuss how the requirements of real-time mobile vision applications impact on tools, architectures and systems.

Keynote: Calin Cascaval, Qualcomm Symphony: Orchestrating Heterogeneity for Power Aware Computing

General purpose as well as integrated processors nowadays have to run programs written in a wide variety of languages with isolation concerns. Dynamic compilation, i.e. generate binary code at run-time, is becoming a viable solution for many usage scenarios, and the goal of this workshop is to present current research and look forward to what is going to happen in this field of growing interest for the coming years.

Scientific challenges are multiple with many inter-relations: program representation (source code, intermediate representation, data sets), fast binary code generation, patches, hardware abstraction, garbage collection, performance observation, performance trade-offs, polymorphism, operating systems.

Chair: Mary Lou Soffa (University of Virginia)

#4: Tongping Liu and Xu Liu. Cheetah: Detecting False Sharing Efficiently and Effectively

#27: Dehao Chen, Xinliang David Li and Tipp Moseley. AutoFDO: Automatic Feedback-directed Optimization for Warehouse-scale Applications

#32: Ivan Jibaja, Ting Cao, Steve Blackburn and Kathryn McKinley. Portable Performance on Asymmetric Multicore Processors

Chair: Dorit Nuzman (Intel)

#53: Probir Roy and Xu Liu. MemTool: A Lightweight Profiler to Guide Structure Splitting

#29: Linchuan Chen, Peng Jiang and Gagan Agrawal. Expoliting Recent SIMD Architectural Advances for Irregular Applications

#59: Hao Zhou and Jingling Xue. Exploiting Mixed SIMD Parallelism by Reducing Data Reorganization Overhead

Chair: Vijay Janapa Reddi (University of Texas)

#52: Raj Barik, Naila Farooqui, Brian Lewis, Chunling Hu and Tatiana Shpeisman. A Black-box Approach to Energy-Aware Scheduling on Integrated CPU-GPU Systems

#5: Christos Margiolas and Michael F.P. O’Boyle. Portable and Transparent Software Managed Scheduling on Accelerators for Fair Resource Sharing

#62: Dong Nguyen and Jongeun Lee. Communication-Aware Mapping of Stream Graphs for Multi-GPU Platforms

#8: Jingyue Wu, Eli Bendersky, Mark Heffernan, Chris Leary, Jacques Pienaar, Bjarke Roune, Rob Springer, Xuetian Weng and Robert Hundt. gpucc: An Open-Source GPGPU Compiler

Chair: Louis-Noël Pouchet (Ohio State University)

#91: Daniele G. Spampinato and Markus Püschel. A Basic Linear Algebra Compiler for Structured Matrices

#38: Lénaïc Bagnères, Oleksandr Zinenko, Stéphane Huot and Cédric Bastoul. Opening Polyhedral Compiler’s Black Box

#64: Gabriel Rodríguez, José M. Andión, Mahmut Kandemir and Juan Tourino. Trace-based Affine Reconstruction of Codes

Chair: Michael O’Boyle (University of Edinburgh)

#42: Mateus Tymburiba, Rubens Emílio and Fernando Pereira. Inference of Peak Density of Indirect Branches to Detect ROP Attacks

#25: Yulei Sui, Peng Di and Jingling Xue. Sparse Flow-Sensitive Pointer Analysis for Multithreaded C Programs

#43: Vitor Paisante, Maroua Maalej, Leonardo Barbosa, Laure Gonnord and Fernando Pereira. Symbolic Range Analysis of Pointers

Chair: Mauricio Breternitz (AMD)

#74: Vassilis Vassiliadis, Jan Riehme, Jens Deussen, Konstantinos Parasyris, Christos D. Antonopoulos, Nikolaos Bellas, Spyros Lalis and Uwe Naumann. Towards Automatic Significance Analysis for Approximate Computing

#17: Kevin Brown, Hyoukjoong Lee, Tiark Rompf, Arvind Sujeeth, Christopher De Sa, Christopher Aberger and Kunle Olukotun. Have Abstraction and Eat Performance Too: Optimized Heterogeneous Computing with Parallel Patterns

#28: Melanie Kambadur and Martha Kim. NRG-Loops: Adjusting Power from Within Applications

Knights Landing Intel Xeon Phi CPU: Path to Parallelism with General Purpose Programming

The demand for high performance will continue to skyrocket in the future, fueled by the drive to solve the challenging problems in scientific world and to provide the horsepower needed to support the compute-hungry use cases that continue to emerge in commercial and consumer space, such as machine learning and deep data analytics. Exploiting parallelism will be crucial in achieving the huge performance gain required to solve these problems. This talk will present the new Xeon Phi Processor, called Knights Landing, which is architected to provide massive amounts of parallelism in a manner that is accessible with general purpose programming. The talk will provide insights into 1) the important architecture features of the processor and 2) the software technology to explore them. It will provide the inside story on the various architecture decisions made on Knights Landing – why we architected the processor the way we did, and on a few programming experience – how the general purpose programming model makes it easy to exploit parallelism on Xeon Phi. It will show measured performance numbers from the Knights Landing silicon on a range of workloads. The talk will conclude with showing the historical trends in architecture and what they mean for software as we extend the trends into the future.

Biography

Avinash Sodani is a Senior Principal Engineer at Intel Corporation and the chief architect of the Xeon-Phi Processor called Knights Landing. He specializes in the field of High Performance Computing (HPC). Previously, he was one of the architects of the 1st generation Core processor, called Nehalem, which has served as a foundation for today’s line of Intel Core processors. Avinash is a recognized expert in computer architecture and has been invited to deliver several keynotes and public talks on topics related to HPC and future of computing. Avinash holds over 20 US Patents and is known for seminal work on the concept of “Dynamic Instruction Reuse”.  He has a PhD and MS in Computer Science from University of Wisconsin-Madison and a B.Tech (Hon’s) in Computer Science from Indian Institute of Technology, Kharagpur in India.

Chair: Aaron Smith (Microsoft)

#45: Soham Chakraborty and Viktor Vafeiadis. Validating Optimizations of Concurrent C/C++ Programs

#85: Ignacio Laguna, Martin Schulz, David F. Richards, Jon Calhoun and Luke Olson. IPAS: Intelligent Protection Against Silent Output Corruption in Scientific Applications

#99: Adarsh Yoga and Santosh Nagarakatte. Atomicity Violation Checker for Task Parallel Programs

Chair: Soo-mook Moon (Seoul National University)

#95: Daniele Cono D’Elia and Camil Demetrescu. Flexible On-Stack Replacement in LLVM

#96: Byron Hawkins, Brian Demsky and Michael Taylor. BlackBox: Lightweight Security Monitoring for COTS Binaries

#69: Toshihiko Koju, Reid Copeland, Motohiro Kawahito and Moriyoshi Ohara. Re-constructing High-Level Information for Language-Specific Binary Re-optimization