The main goal of this half-day workshop is to bring together researchers and practitioners with the aim of stimulating the exchange of ideas and experiences on the potential and limits of Architectural and MicroArchitectural Support for Binary Translation (hence the acronym AMAS-BT). The key focus is on challenges and opportunities for such assistance and opening new avenues of research. A secondary goal is to enable dissemination of hitherto unpublished Important Dates

In this workshop the attendees will have the opportunity to delve into the topic of application auto-tuning, presented by developers and performance engineers from the AutoTune project. This workshop will present the theory behind auto-tuning, focusing on the conceptual basis and discussing the latest advancements in the field within the AutoTune project, whereas the related tutorial in the afternoon (Code Auto-Tuning with the Periscope Tuning Framework) will provide a practical perspective to auto-tuning, exemplifying with use cases how to best harness and tailor performance analysers to tune real applications.

Salad

Assorted Mixed Greens with Poached Pear, Sweet Onion Mustard Dressing on the side.

Entrées

Chicken Breast with Mushrooms topped with Cream Sauce.

Salmon with Capers topped with Lemon-Butter Sauce.

Quinoa Comfit

Veggie Moussaka

Dessert

Strawberry or Chocolate Mousse

Many-core architectures such as mobile SOCs or GPGPUs are quickly becoming the norm in computing devices and consumer electronics. The community sees this development as essential in sustaining the exponential growth of performance in an energy efficient way, but at present there is no consensus on how software can make best use of it. Developing parallel applications often starts with an existing sequential implementation. A key problem is how to discover the parallelism potentially available and then convert it into a form that can be exploited. Once we have a parallel implementation, its performance and energy efficiency largely depend on how it is mapped to the available hardware. Given that hardware is increasingly diverse and heterogeneous and that in the era of dark silicon energy efficiency affects the availability of hardware, how can this re-mapping be best achieved. Solutions to these two problems form the core topic of the workshop. With novel research papers and expert invited speakers from both industry and academia, this workshop aims at examining different solutions to these problems and includes (but is not limited to):

• programming languages and models
• compilers and tools
• runtime systems
• operating systems
• binary translation
• combinations of the above

for homogeneous, heterogeneous multi-core and many-core based systems.

Salad

Classic Caesar Salad with Dressing on the side.

Entrées

Chicken Piccata

Seafood Kebab with Salsa Fresca

Tomatoes alla Parmigiana

Veggie Lasagna

Steamed Rice

Dessert

Tiramisu

Abstract: By end of the decade we expect over 30 billion intelligent devices connected to the internet, resulting in unprecedented amounts of data. At the same time, scaling of the memory technologies that are at the foundation of computing today will significantly slow down. We will need transformational changes to the way in which we collect, process, store, and analyze that data. Not everyone realizes that these changes will revolutionize the way in which we architect and program computing systems. This talk will discuss the technology trends, the implications to software and programming, and what we are doing at HP to address some of the challenges. Starting from the emerging non-volatile devices, it will cover how they will enable flattening and re-architecting the memory hierarchy. Then, it will dive into the implications to software, discussing how file systems, databases and explicit applications can take advantage of large, flat and persistent memory spaces.

Biography: Paolo Faraboschi is an HP Fellow at HP Labs. His interests are at the intersection of system architecture and software. He is currently working on TheMachine project, researching how we can build better systems around non-volatile memory. In the last five years, he worked on low-energy servers and HP project Moonshot. From 2004 to 2009, at HPL in Barcelona, he led a research activity on scalable system-level simulation and modeling. From 1995 to 2003, at HPL Cambridge, he was the principal architect of the Lx/ST200 family of VLIW cores, widely used in video SoCs and HP’s printers. Paolo is an IEEE Fellow and an active member of the computer architecture community: guest co-editor of IEEE Micro TopPicks 2012, Program co-Chair for HiPEAC10 (2010), MICRO41 (2008) and MICRO34 (2001). He holds 25 patents and co-authored the book “Embedded Computing: a VLIW approach to architecture, compiler end tools”. Before joining HP in 1994, he received a Ph.D. in EECS from the University of Genoa, Italy.

Latin Buffet

Fresh Corn and Flour Tortillas

Mexican Vegetable Soup

Jicama and Watermelon Salad

Grilled Chayote Squash and Tomato Salad With Lemon Vinaigrette

Cheese Enchiladas, Chipotle Tomato Sauce, Queso Blanco Arroz Con Pollo, Chicken, Rice, Roasted Corn, Peas

Achiote Grilled Skirt Steak With Cilantro Chimichurri

Black Beans

Dulce De Leche Cake

Fresh Baked Cinnamon Cookies

Royal Cup Dakota Roast Coffee, Decaffeinated, Hot Tea and Iced Tea

Pan Pacific Buffet

Spinach and Tofu Soup

Spicy Firecracker Spinach, Orange Sesame Dressing

Tofu Bean Curd and Cucumber Salad

Lemon Grass Basil Scented Basa With Coconut Green Curry Sauce

Orange Peel Chicken and Green Beans

Pork Pot Stickers

Stir Fried Vegetables

California Brown Rice

Mango Coconut Mousse

Lemon Burst Macaroon Bars

Royal Cup Dakota Roast Coffee, Decaffeinated, Hot Tea and Iced Tea

Abstract: I will describe a decade-long, multi-disciplinary, multi-institutional effort spanning neuroscience, supercomputing, and nanotechnology to build and demonstrate a brain-inspired computer and describe the architecture, programming model, and applications. For more information, see: modha.org.

Biography: Dr. Dharmendra S. Modha is an IBM Fellow and IBM Chief Scientist for Brain-inspired Computing. He is a cognitive computing pioneer who envisioned and now leads a highly successful effort to develop brain-inspired computers. The groundbreaking project, SyNAPSE, funded by DARPA to the tune of $53.5M, is multi-disciplinary, multi-national, multi-institutional and has had worldwide scientific impact. Its resulting revolutionary computing architecture and ecosystem break from the prevailing von Neumann paradigm and constitute a foundation for new classes of ultra-low-power, compact, real-time, multi-modal sensorimotor information technology systems. Dr. Modha has also made significant contributions to IBM businesses via innovations in caching mechanisms for storage controllers, clustering algorithms for services, and coding theory for disk drives. His work has been featured in Economist, Science, New York Times, BBC, Discover, MIT Technology Report, Associated Press, Popular Mechanics, Communications of the ACM, Forbes, Fortune, and IEEE Spectrum amongst thousands of media mentions. Author of over 60 papers and inventor of over 100 patents, he has won ACM’s Gordon Bell Prize, USENIX/FAST Test of Time Award, Best Paper Awards at ASYNC and IDEMI, First Place, Science/NSF International Science & Engineering Visualization Challenge, and is a Fellow of IEEE and World Technology Network. In 2013 and 2014, he was named as Best of IBM. On their 40th Anniversary, EE Times named Dr. Modha amongst 10 Electronics Visionaries to Watch. Dr. Modha received BTech from IIT Bombay in 1990 and PhD from UCSD in 1995.

Abstract: Languages, compilers, and computer-aided design tools will be essential for scalable quantum computing, which promises an exponential leap in our ability to execute complex tasks. LIQUi|> is a modular software architecture designed to simulate and control quantum hardware. It enables easy programming, compilation, and simulation of quantum algorithms and circuits, and is independent of a specific quantum architecture. This talk will focus on simulation of quantum algorithms in Quantum Chemistry and Materials as well as Factoring, Quantum Error Correction and compilation for hardware implementations (http://arxiv.org/abs/1402.4467).

Biography: Dave came to Microsoft in 1995 and helped create the “Blender” (digital video post-production facility). He designed and worked on a Broadband MSN offering when he became architect for the Handheld PC v1 & v2 as well as AutoPC v1 and Pocket PC v1. He moved to Intelligent Interface Technology and resurrected SHRDLU for Natural Language research as well as building a state of the art Neural Network based Speech Recognition system. For the Mobile Devices Division he implemented secure DRM on e-books and Pocket PCs. He created and was director of ePeriodicals before taking on the role of Architect for Emerging Technologies. This lead to starting the Machine Learning Incubation Team and then architect for Parallel Computing Technology Strategy working on Big Data and now Quantum Computing. He has over 20 patents for Microsoft and 9 Ship-It awards. He started coding professionally in 1973, worked in the AI labs at CMU while obtaining a BSEE and MSIA and was at DEC for 13 years (ask him about DIDDLY sometime ;).