Event-Flow Graphs for Efficient Path-Sensitive Analyses
Ahmed Tamrawi (Iowa State University)
Intelligent Heuristic Construction with Active Learning
William Ogilvie (University of Edinburgh)
An Intermediate Language for DSLs Providing Support for Automatic Optimization and OpenCL Code Generation
Riyadh Baghdadi (Inria and KU Leuven)
Employing Code Generators as De-code Generators: A Novel Approach for Assembly to IR Translation
Niranjan Hasabnis (Stony Brook University)
Reducing Memory Buffering Overhead in Software Thread-Level Speculation
Zhen Cao (McGill)
Bitwidth Analysis and Optimization Using Dynamic Compilation Strategies
Kirshanthan Sundararajah (University of Moratuwa, Sri Lanka)
Auto-tuning the HotSpot JVM
Tharindu Rusira, Milinda Fernando, Chalitha Perera, and Chamara Philips (University of Moratuwa, Sri Lanka)
Abstract: By end of the decade we expect over 30 billion intelligent devices connected to the internet, resulting in unprecedented amounts of data. At the same time, scaling of the memory technologies that are at the foundation of computing today will significantly slow down. We will need transformational changes to the way in which we collect, process, store, and analyze that data. Not everyone realizes that these changes will revolutionize the way in which we architect and program computing systems. This talk will discuss the technology trends, the implications to software and programming, and what we are doing at HP to address some of the challenges. Starting from the emerging non-volatile devices, it will cover how they will enable flattening and re-architecting the memory hierarchy. Then, it will dive into the implications to software, discussing how file systems, databases and explicit applications can take advantage of large, flat and persistent memory spaces.
Biography: Paolo Faraboschi is an HP Fellow at HP Labs. His interests are at the intersection of system architecture and software. He is currently working on TheMachine project, researching how we can build better systems around non-volatile memory. In the last five years, he worked on low-energy servers and HP project Moonshot. From 2004 to 2009, at HPL in Barcelona, he led a research activity on scalable system-level simulation and modeling. From 1995 to 2003, at HPL Cambridge, he was the principal architect of the Lx/ST200 family of VLIW cores, widely used in video SoCs and HP’s printers. Paolo is an IEEE Fellow and an active member of the computer architecture community: guest co-editor of IEEE Micro TopPicks 2012, Program co-Chair for HiPEAC10 (2010), MICRO41 (2008) and MICRO34 (2001). He holds 25 patents and co-authored the book “Embedded Computing: a VLIW approach to architecture, compiler end tools”. Before joining HP in 1994, he received a Ph.D. in EECS from the University of Genoa, Italy.
Improving GPGPU Energy-Efficiency through Concurrent Kernel Execution and DVFS
Qing Jiao (National University of Singapore), Mian Lu and Huynh Phung Huynh (Institute of High Performance Computing, A*STAR, Singapore), and Tulika Mitra (National University of Singapore)
Characterizing and Enhancing Global Memory Data Coalescing on GPUs
Naznin Fauzia, Louis-Noel Pouchet, and P Sadayappan (The Ohio State University, Columbus)
Automatic Data Placement into GPU On-chip Memory Resources
Chao Li (North Carolina State University), Yi Yang (NEC labs), and Zhen Lin and Huiyang Zhou (North Carolina State University)
Kyle Dewey, Vineeth Kashyap, and Ben Hardekopf (University of California, Santa Barbara)
On Performance Debugging of Unnecessary Lock Contentions on Multicore Processors: A Replay-based Approach
Long Zheng and Xiaofei Liao (Huazhong University of Science and Technology, China), Bingsheng He (Nanyang Technological University, Singapore), and Song Wu and Hai Jin (Huazhong University of Science and Technology, China)
Jithendra Srinivas (Intel), Wei Ding, and Mahmut Kandemir (Penn State)
Approximating Flow-Sensitive Pointer Analysis Using Frequent Itemset Mining
Vaivaswatha Nagaraj and R. Govindarajan (Indian Institute of Science, Bangalore)
HELIX-UP: Relaxing Program Semantics to Unleash Parallelization
Simone Campanoni, Glenn Holloway, Gu-Yeon Wei, and David Brooks (Harvard University)
HERMES: A Fast Cross-ISA Binary Translator with Post-Optimization
Xiaochun Zhang (Institute of Computing Technology, Chinese Academy of Science), Qi Guo (Carnegie Mellon University), and Yunji Chen, Tianshi Chen, and Weiwu Hu (Institute of Computing Technology, Chinese Academy of Science)
Locality-Centric Thread Scheduling for Bulk-synchronous Programming Models on CPU Architectures
Hee-Seok Kim and Izzat El Hajj (University of Illinois at Urbana-Champaign), John Stratton (MulticoreWare Inc.), and Steven Lumetta and Wen-mei Hwu (University of Illinois at Urbana-Champaign)
Branch Prediction and the Performance of Interpreters – Don’t Trust Folklore
Erven Rohou, Bharath Narasimha Swamy, and André Seznec (Inria, France)
Optimizing the flash-RAM energy trade-off in deeply embedded systems
James Pallister, Kerstin Eder, and Simon J. Hollis (University of Bristol)
EMEURO: A Framework for Generating Multi-Purpose Accelerators via Deep Learning
Lawrence McAfee and Kunle Olukotun (Stanford University)
Optimizing and Auto-Tuning Scale-Free Sparse Matrix-Vector Multiplication on Intel Xeon Phi
Wai Teng Tang (Institute of High Performance Computing, A*STAR, Singapore), Ruizhe Zhao (Peking University, China), Mian Lu (Institute of High Performance Computing, A*STAR, Singapore), Yun Liang (Peking University, China), Huynh Phung Huynh (Institute of High Performance Computing, A*STAR, Singapore), Xibai Li (Peking University, China), and Rick Siow Mong Goh (Institute of High Performance Computing, A*STAR, Singapore)
Data Provenance Tracking for Concurrent Programs
Brandon Lucia (Carnegie Mellon University) and Luis Ceze (University of Washington)
Locality Aware Concurrent Start for Stencil Applications
Sunil Shrestha (University of Delaware), Joseph Manzano, Andres Marquez, and John Feo (Pacific Northwest National Laboratory), and Guang R. Gao (University of Delaware)
Abstract: I will describe a decade-long, multi-disciplinary, multi-institutional effort spanning neuroscience, supercomputing, and nanotechnology to build and demonstrate a brain-inspired computer and describe the architecture, programming model, and applications. For more information, see: modha.org.
Biography: Dr. Dharmendra S. Modha is an IBM Fellow and IBM Chief Scientist for Brain-inspired Computing. He is a cognitive computing pioneer who envisioned and now leads a highly successful effort to develop brain-inspired computers. The groundbreaking project, SyNAPSE, funded by DARPA to the tune of $53.5M, is multi-disciplinary, multi-national, multi-institutional and has had worldwide scientific impact. Its resulting revolutionary computing architecture and ecosystem break from the prevailing von Neumann paradigm and constitute a foundation for new classes of ultra-low-power, compact, real-time, multi-modal sensorimotor information technology systems. Dr. Modha has also made significant contributions to IBM businesses via innovations in caching mechanisms for storage controllers, clustering algorithms for services, and coding theory for disk drives. His work has been featured in Economist, Science, New York Times, BBC, Discover, MIT Technology Report, Associated Press, Popular Mechanics, Communications of the ACM, Forbes, Fortune, and IEEE Spectrum amongst thousands of media mentions. Author of over 60 papers and inventor of over 100 patents, he has won ACM’s Gordon Bell Prize, USENIX/FAST Test of Time Award, Best Paper Awards at ASYNC and IDEMI, First Place, Science/NSF International Science & Engineering Visualization Challenge, and is a Fellow of IEEE and World Technology Network. In 2013 and 2014, he was named as Best of IBM. On their 40th Anniversary, EE Times named Dr. Modha amongst 10 Electronics Visionaries to Watch. Dr. Modha received BTech from IIT Bombay in 1990 and PhD from UCSD in 1995.
Getting in Control of Your Control Flow with Control-Data Isolation
William Arthur (University of Michigan), Ben Mehne (University of California – Berkeley), and Reetuparna Das and Todd Austin (University of Michigan)
Checking Correctness of Code Generator Architecture Specifications
Niranjan Hasabnis, R. Sekar, and Rui Qiao (Stony Brook University)
Snapshot-based Loading-Time Acceleration for Web Applications
JinSeok Oh and Soo-Mook Moon (Seoul National University)
We will be attending a private showing of Beach Blanket Babylon from 5:45 pm – 7:15 pm along with PPoPP.
After the show you will have time for dinner on your own with colleagues and new friends.
Buses will leave the Marriott at 4:10 pm and return at 7:15 pm and 10:15 pm.
If you wish to return via public transporation, you can do so via a combination of walking, trolley and BART in around one and half hours.
The North Beach area of San Francisco is known for its Italian heritage.
Here is a link to great pizza places on Yelp and a list of restaraunts close to the theatre.
478 Green @ Grant
Until 10:30 pm
Distance to theatre: 2 blocks
430 Columbus near Green
Until 1 am
Distance to theatre: 1 1/2 blocks
1600 Powell St. @ Green
Until 10:30 pm
Distance to Theatre: 1/4 Block
1652 Stockton St. near Filbert
|$$$ NEW AMERICAN
Until 10 pm
Distance to theatre: 2 1/2 blocks
659 Columbus @ Powell
Until 10 pm
Distance to theatre: 2 1/2 blocks
401 Columbus Ave. @ Vallejo
Until 11 pm
Distance to theatre: 2 blocks
515 Broadway @ Columbus
|LATIN AMERICAN WINE BAR
Tapas (no full meals)
Distance to theatre: 3 1/2 blocks
Abstract: Languages, compilers, and computer-aided design tools will be essential for scalable quantum computing, which promises an exponential leap in our ability to execute complex tasks. LIQUi|> is a modular software architecture designed to simulate and control quantum hardware. It enables easy programming, compilation, and simulation of quantum algorithms and circuits, and is independent of a specific quantum architecture. This talk will focus on simulation of quantum algorithms in Quantum Chemistry and Materials as well as Factoring, Quantum Error Correction and compilation for hardware implementations (http://arxiv.org/abs/1402.4467).
Biography: Dave came to Microsoft in 1995 and helped create the “Blender” (digital video post-production facility). He designed and worked on a Broadband MSN offering when he became architect for the Handheld PC v1 & v2 as well as AutoPC v1 and Pocket PC v1. He moved to Intelligent Interface Technology and resurrected SHRDLU for Natural Language research as well as building a state of the art Neural Network based Speech Recognition system. For the Mobile Devices Division he implemented secure DRM on e-books and Pocket PCs. He created and was director of ePeriodicals before taking on the role of Architect for Emerging Technologies. This lead to starting the Machine Learning Incubation Team and then architect for Parallel Computing Technology Strategy working on Big Data and now Quantum Computing. He has over 20 patents for Microsoft and 9 Ship-It awards. He started coding professionally in 1973, worked in the AI labs at CMU while obtaining a BSEE and MSIA and was at DEC for 13 years (ask him about DIDDLY sometime ;).
PSLP: Padded SLP Automatic Vectorization
Vasileios Porpodas (University of Cambridge), Alberto Magni (University of Edinburgh), and Timothy M. Jones (University of Cambridge)
A Graph-Based Higher-Order Intermediate Representation
Roland Leißa, Marcel Köster, and Sebastian Hack (Saarland University)
Scalable Conditional Induction Variable (CIV) Analysis
Cosmin E. Oancea (University of Copenhagen) and Lawrence Rauchwerger (Texas A&M University)
Optimizing Binary Translation for Dynamically Generated Code
Byron Hawkins and Brian Demsky (University of California, Irvine) and Derek Bruening and Qin Zhao (Google, Inc.)
MemorySanitizer: fast detector of uninitialized memory use in C++
Evgeniy Stepanov and Konstantin Serebryany (Google)