The main goal of this half-day workshop is to bring together researchers and practitioners with the aim of stimulating the exchange of ideas and experiences on the potential and limits of Architectural and MicroArchitectural Support for Binary Translation (hence the acronym AMAS-BT). The key focus is on challenges and opportunities for such assistance and opening new avenues of research. A secondary goal is to enable dissemination of hitherto unpublished Important Dates
In this workshop the attendees will have the opportunity to delve into the topic of application auto-tuning, presented by developers and performance engineers from the AutoTune project. This workshop will present the theory behind auto-tuning, focusing on the conceptual basis and discussing the latest advancements in the field within the AutoTune project, whereas the related tutorial in the afternoon (Code Auto-Tuning with the Periscope Tuning Framework) will provide a practical perspective to auto-tuning, exemplifying with use cases how to best harness and tailor performance analysers to tune real applications.
Salad
Assorted Mixed Greens with Poached Pear, Sweet Onion Mustard Dressing on the side.
Entrées
Chicken Breast with Mushrooms topped with Cream Sauce.
Salmon with Capers topped with Lemon-Butter Sauce.
Quinoa Comfit
Veggie Moussaka
Dessert
Strawberry or Chocolate Mousse
Many-core architectures such as mobile SOCs or GPGPUs are quickly becoming the norm in computing devices and consumer electronics. The community sees this development as essential in sustaining the exponential growth of performance in an energy efficient way, but at present there is no consensus on how software can make best use of it. Developing parallel applications often starts with an existing sequential implementation. A key problem is how to discover the parallelism potentially available and then convert it into a form that can be exploited. Once we have a parallel implementation, its performance and energy efficiency largely depend on how it is mapped to the available hardware. Given that hardware is increasingly diverse and heterogeneous and that in the era of dark silicon energy efficiency affects the availability of hardware, how can this re-mapping be best achieved. Solutions to these two problems form the core topic of the workshop. With novel research papers and expert invited speakers from both industry and academia, this workshop aims at examining different solutions to these problems and includes (but is not limited to):
- programming languages and models
- compilers and tools
- runtime systems
- operating systems
- binary translation
- combinations of the above
for homogeneous, heterogeneous multi-core and many-core based systems.
Salad
Classic Caesar Salad with Dressing on the side.
Entrées
Chicken Piccata
Seafood Kebab with Salsa Fresca
Tomatoes alla Parmigiana
Veggie Lasagna
Steamed Rice
Dessert
Tiramisu
Graduate Category
Event-Flow Graphs for Efficient Path-Sensitive Analyses
Ahmed Tamrawi (Iowa State University)
Intelligent Heuristic Construction with Active Learning
William Ogilvie (University of Edinburgh)
An Intermediate Language for DSLs Providing Support for Automatic Optimization and OpenCL Code Generation
Riyadh Baghdadi (Inria and KU Leuven)
Employing Code Generators as De-code Generators: A Novel Approach for Assembly to IR Translation
Niranjan Hasabnis (Stony Brook University)
Reducing Memory Buffering Overhead in Software Thread-Level Speculation
Zhen Cao (McGill)
Bitwidth Analysis and Optimization Using Dynamic Compilation Strategies
Kirshanthan Sundararajah (University of Moratuwa, Sri Lanka)
Undergraduate Category
Auto-tuning the HotSpot JVM
Tharindu Rusira, Milinda Fernando, Chalitha Perera, and Chamara Philips (University of Moratuwa, Sri Lanka)
Improving GPGPU Energy-Efficiency through Concurrent Kernel Execution and DVFS
Qing Jiao (National University of Singapore), Mian Lu and Huynh Phung Huynh (Institute of High Performance Computing, A*STAR, Singapore), and Tulika Mitra (National University of Singapore)
Characterizing and Enhancing Global Memory Data Coalescing on GPUs
Naznin Fauzia, Louis-Noel Pouchet, and P Sadayappan (The Ohio State University, Columbus)
Automatic Data Placement into GPU On-chip Memory Resources
Chao Li (North Carolina State University), Yi Yang (NEC labs), and Zhen Lin and Huiyang Zhou (North Carolina State University)
Latin Buffet
Fresh Corn and Flour Tortillas
Mexican Vegetable Soup
Jicama and Watermelon Salad
Grilled Chayote Squash and Tomato Salad With Lemon Vinaigrette
Cheese Enchiladas, Chipotle Tomato Sauce, Queso Blanco Arroz Con Pollo, Chicken, Rice, Roasted Corn, Peas
Achiote Grilled Skirt Steak With Cilantro Chimichurri
Black Beans
Dulce De Leche Cake
Fresh Baked Cinnamon Cookies
Royal Cup Dakota Roast Coffee, Decaffeinated, Hot Tea and Iced Tea
A Parallel Abstract Interpreter for JavaScript
Kyle Dewey, Vineeth Kashyap, and Ben Hardekopf (University of California, Santa Barbara)
On Performance Debugging of Unnecessary Lock Contentions on Multicore Processors: A Replay-based Approach
Long Zheng and Xiaofei Liao (Huazhong University of Science and Technology, China), Bingsheng He (Nanyang Technological University, Singapore), and Song Wu and Hai Jin (Huazhong University of Science and Technology, China)
Reactive Tiling
Jithendra Srinivas (Intel), Wei Ding, and Mahmut Kandemir (Penn State)
Approximating Flow-Sensitive Pointer Analysis Using Frequent Itemset Mining
Vaivaswatha Nagaraj and R. Govindarajan (Indian Institute of Science, Bangalore)
HELIX-UP: Relaxing Program Semantics to Unleash Parallelization
Simone Campanoni, Glenn Holloway, Gu-Yeon Wei, and David Brooks (Harvard University)
HERMES: A Fast Cross-ISA Binary Translator with Post-Optimization
Xiaochun Zhang (Institute of Computing Technology, Chinese Academy of Science), Qi Guo (Carnegie Mellon University), and Yunji Chen, Tianshi Chen, and Weiwu Hu (Institute of Computing Technology, Chinese Academy of Science)
Locality-Centric Thread Scheduling for Bulk-synchronous Programming Models on CPU Architectures
Hee-Seok Kim and Izzat El Hajj (University of Illinois at Urbana-Champaign), John Stratton (MulticoreWare Inc.), and Steven Lumetta and Wen-mei Hwu (University of Illinois at Urbana-Champaign)
Branch Prediction and the Performance of Interpreters – Don’t Trust Folklore
Erven Rohou, Bharath Narasimha Swamy, and André Seznec (Inria, France)
Optimizing the flash-RAM energy trade-off in deeply embedded systems
James Pallister, Kerstin Eder, and Simon J. Hollis (University of Bristol)
EMEURO: A Framework for Generating Multi-Purpose Accelerators via Deep Learning
Lawrence McAfee and Kunle Olukotun (Stanford University)
Optimizing and Auto-Tuning Scale-Free Sparse Matrix-Vector Multiplication on Intel Xeon Phi
Wai Teng Tang (Institute of High Performance Computing, A*STAR, Singapore), Ruizhe Zhao (Peking University, China), Mian Lu (Institute of High Performance Computing, A*STAR, Singapore), Yun Liang (Peking University, China), Huynh Phung Huynh (Institute of High Performance Computing, A*STAR, Singapore), Xibai Li (Peking University, China), and Rick Siow Mong Goh (Institute of High Performance Computing, A*STAR, Singapore)
Data Provenance Tracking for Concurrent Programs
Brandon Lucia (Carnegie Mellon University) and Luis Ceze (University of Washington)
Locality Aware Concurrent Start for Stencil Applications
Sunil Shrestha (University of Delaware), Joseph Manzano, Andres Marquez, and John Feo (Pacific Northwest National Laboratory), and Guang R. Gao (University of Delaware)
Pan Pacific Buffet
Spinach and Tofu Soup
Spicy Firecracker Spinach, Orange Sesame Dressing
Tofu Bean Curd and Cucumber Salad
Lemon Grass Basil Scented Basa With Coconut Green Curry Sauce
Orange Peel Chicken and Green Beans
Pork Pot Stickers
Stir Fried Vegetables
California Brown Rice
Mango Coconut Mousse
Lemon Burst Macaroon Bars
Royal Cup Dakota Roast Coffee, Decaffeinated, Hot Tea and Iced Tea
Getting in Control of Your Control Flow with Control-Data Isolation
William Arthur (University of Michigan), Ben Mehne (University of California – Berkeley), and Reetuparna Das and Todd Austin (University of Michigan)
Checking Correctness of Code Generator Architecture Specifications
Niranjan Hasabnis, R. Sekar, and Rui Qiao (Stony Brook University)
Snapshot-based Loading-Time Acceleration for Web Applications
JinSeok Oh and Soo-Mook Moon (Seoul National University)
We will be attending a private showing of Beach Blanket Babylon from 5:45 pm – 7:15 pm along with PPoPP.
After the show you will have time for dinner on your own with colleagues and new friends.
Transportation
Buses will leave the Marriott at 4:10 pm and return at 7:15 pm and 10:15 pm.
If you wish to return via public transporation, you can do so via a combination of walking, trolley and BART in around one and half hours.
Dining
The North Beach area of San Francisco is known for its Italian heritage.
Here is a link to great pizza places on Yelp and a list of restaraunts close to the theatre.
Bocce Café 478 Green @ Grant (415) 981-2044 www.boccecafe.com |
$$ ITALIAN Until 10:30 pm Distance to theatre: 2 blocks |
Calzone’s 430 Columbus near Green (415) 397-3600 www.calzonesf.com |
$$ ITALIAN Until 1 am Distance to theatre: 1 1/2 blocks |
Capp’s Corner 1600 Powell St. @ Green (415) 989-2589 www.cappscorner.com |
$$ ITALIAN Until 10:30 pm Distance to Theatre: 1/4 Block |
Park Tavern 1652 Stockton St. near Filbert (415) 989-7300 www.parktavernsf.com |
$$$ NEW AMERICAN Until 10 pm Distance to theatre: 2 1/2 blocks |
Piazza Pellegrini 659 Columbus @ Powell (415) 397-7355 www.piazzapellegrini.com |
$$ ITALIAN Until 10 pm Distance to theatre: 2 1/2 blocks |
Trattoria Pinocchio 401 Columbus Ave. @ Vallejo (415) 392-1472 www.trattoriapinocchio.com |
$$ ITALIAN Until 11 pm Distance to theatre: 2 blocks |
Antologia Vinoteca 515 Broadway @ Columbus (415) 274-8423 www.antologiasf.com |
LATIN AMERICAN WINE BAR Tapas (no full meals) Until midnight Distance to theatre: 3 1/2 blocks |
PSLP: Padded SLP Automatic Vectorization
Vasileios Porpodas (University of Cambridge), Alberto Magni (University of Edinburgh), and Timothy M. Jones (University of Cambridge)
A Graph-Based Higher-Order Intermediate Representation
Roland Leißa, Marcel Köster, and Sebastian Hack (Saarland University)
Scalable Conditional Induction Variable (CIV) Analysis
Cosmin E. Oancea (University of Copenhagen) and Lawrence Rauchwerger (Texas A&M University)
Optimizing Binary Translation for Dynamically Generated Code
Byron Hawkins and Brian Demsky (University of California, Irvine) and Derek Bruening and Qin Zhao (Google, Inc.)
MemorySanitizer: fast detector of uninitialized memory use in C++
Evgeniy Stepanov and Konstantin Serebryany (Google)