WISH - Workshop on Infrastructures for Software/Hardware co-design

Final Program

	Sunday, April 25th
Keynote
8:30	"Robust and Fast Dynamic Systems"
	Robert Cohn - Senior Principal Engineer - Intel Corp.
Section	1
9:35	"A Proposal for Hardware-Assisted Arithmetic Overflow Detection for Array and Bitfield Operations"
	Darek Mihocka [Intel], Jens Troeger [Intel]
	Break (at 10:00, for 30min)
Section	2
10:30	"Profiling the Dynamic Behavior of Nested Loops Using the Loop-Call Context Tree"
	Yukinori Sato [Japan Advanced Institute of Science & Technology], Tadao Nakamura [Keio University]
10:55	"Chimpp: A Modular Programming and Simulation Environment for Reconfigurable Networking Hardware"
	Erik Rubow [UCSD], Rick McGeer [HP Labs], Jeff Mogul [HP Labs], Amin Vahdat [UCSD]
11:20	"A Model-Based Design Approach to Hardware/Software Co-Design at UAHuntsville"
	Rhonda Gaede, David Moody, Michael Adderley, Charles Fulks, Laurie Joiner, Jeffrey Kulick
11:45	"MORE: A Tool for Co-optimization in Linear Algebra"
	Eric Robinson*, Nadya Bliss*, Sanjeev Mohindra*, Julie Mullen *[MIT Lincoln Laboratory], Una-May O'Reilly [MIT]
12:10	Lunch

About WISH

A major hindrance to the development of co-designed hardware and software systems is the availability of fast, accurate, and reliable infrastructures for performance evaluation and analysis. Simultaneously varying both the software and hardware components of a system introduces complexities which render traditional evaluation methodologies unusable.

Traditional evaluation methodologies assume that either the hardware or the software components of a system are fixed. For example, an accepted methodology for evaluating the effectiveness of a compiler optimization is to compare the execution of two differently compiled binaries on the same hardware. Likewise, an accepted methodology for evaluating microarchitectural hardware changes has been to measure relatively short, but representative, samples of the same program's execution with multiple configurations of a detailed timing simulator.

Nonetheless, the co-design of hardware and software systems is being pursued as part of many industry and academic projects. Researchers have therefore been forced to build their own custom infrastructures and invent methodologies to demonstrate the viability of their ideas. The purpose of this workshop is for experienced practitioners in this area to share their gained expertise and knowledge to a wider audience in the hopes of broadening community understanding. Identifying readily-available building blocks and tools, as well as opportunities for further improvements in this area are the goals of this workshop.

Topics of interest include, but are not limited to:

• Trace-based and simulation-based infrastructures
• FPGA-based prototyping
• Performance analysis tools and profiling techiques
• Algorithms and representations for co-design
• Design and optimization of novel architectures
• System design
• Language support for dynamic optimization
• Software to hardware mapping
• Novel methodologies for evaluating co-designed:
• Mobile environments
• Virtual execution environments
• Dynamic optimization techniques
• Static compilation techniques
• Graphics systems
• Memory systems, including transactional and consistency models
• Parallelization detection/exploitation techniques

Important Dates

• February 28^th March 14^th 2010 (midnight PST): Extended Abstracts Due
• March 21^th April 4^th 2010: Notification of Acceptance
• April 11^th 2010 (midnight PST): Final version of 20 minute presentation due
• April 25^th 2010: Workshop date

General Chair

Anne Holler, VMware

Program Co-Chairs

Edson Borin, Intel
Uma Srinivasan, Intel

Program Committee

Anne Holler, VMware
Jim Callister, Intel
Nadya Bliss, MIT Lincoln Laboratory
Richard Johnson, NVIDIA
Naveen Kumar, Intel
Shih-Wei Liao, Google
Yukinori Sato, Japan Advanced Institute of Science and Technology (JAIST)
Lacky Shah, NVIDIA