Many-core architectures such as mobile SOCs or GPGPUs are quickly becoming the norm in computing devices and consumer electronics. The community sees this development as essential in sustaining the exponential growth of performance in an energy efficient way, but at present there is no consensus on how software can make best use of it. Developing parallel applications often starts with an existing sequential implementation. A key problem is how to discover the parallelism potentially available and then convert it into a form that can be exploited. Once we have a parallel implementation, its performance and energy efficiency largely depend on how it is mapped to the available hardware. Given that hardware is increasingly diverse and heterogeneous and that in the era of dark silicon energy efficiency affects the availability of hardware, how can this re-mapping be best achieved. Solutions to these two problems form the core topic of the workshop. With novel research papers and expert invited speakers from both industry and academia, this workshop aims at examining different solutions to these problems and includes (but is not limited to):

• programming languages and models
• compilers and tools
• runtime systems
• operating systems
• binary translation
• combinations of the above

for homogeneous, heterogeneous multi-core and many-core based systems.