Altera: Compiling OpenCL to a streaming dataflow architecture on FPGAs

When:
February 8, 2015 @ 8:30 am – 12:00 pm
2015-02-08T08:30:00-08:00
2015-02-08T12:00:00-08:00
Where:
Irvine
Contact:
Deshanand Singh (Altera) and Doris Chen (Altera)

In recent years, Field-Programmable Gate Arrays have become extremely powerful computational platforms that can efficiently solve many complex problems. Modern FPGAs comprise effectively millions of programmable elements, signal processing elements and high-speed interfaces, all of which are necessary to deliver a complete solution. The power of FPGAs is unlocked via low-level programming languages such as VHDL and Verilog, which allow designers to explicitly specify the behavior of each programmable element. While these languages provide a means to create highly efficient logic circuits, they are akin to “assembly language” programming for modern processors. This is a serious limiting factor for both productivity and the adoption of FPGAs on a wider scale.

In this tutorial, we use the OpenCL language to explore techniques that allow us to program FPGAs at a level of abstraction closer to traditional software-centric approaches. OpenCL is an industry standard parallel language based on ‘C’ that offers numerous advantages that enable designers to take full advantage of the capabilities offered by FPGAs, while providing a high-level design entry language that is familiar to a wide range of programmers.

The challenge of mapping a ‘C’ based language to FPGAs is that these languages all have implicit assumptions that the underlying architecture executing these programs is a processor based architecture. Processors are characterized by a sequence of instructions that control a datapath that manipulates data values stored in a memory. Conversely, FPGA architectures are more suited to implementing spatial computing circuits where data flows in a pipelined fashion from one functional unit to the next until computations are complete. Data can be transferred efficiently by wires, registers or FIFOs without always resorting to external storage. This tutorial will explore compiler optimizations and code generation techniques that can transform sequential programs into efficient streaming dataflow circuits for FPGAs. We will examine specific case studies of DSP filters, image processing and mathematical computations to demonstrate how these techniques can be applied to real world examples.