Third Workshop on Explicitly Parallel Instruction Computing Architectures and Compiler Technology (EPIC-3)

PROGRAM (Sunday, March 21^st 2004)

1:00 PM Introduction

1:05 PM Keynote: The Future of the EPIC Architecture

Dan Connors (Univ of Colorado, Boulder)

1:45 PM Session 1: Architecture Research

q EPIC's future: exploring the space between in- and out-of-order Slides

Ronald Barnes, John Sias, Wei-mei Hwu (Univ of Illinois, Urbana-Champaign)

q Instruction Scheduling for Static Placement, Dynamic Issue (SPDI) ArchitectureSlides

Ramadass Nagarajan, Doug Burger, Kathryn S. McKinley, Calvin Lin,

Stephen W. Keckler (Univ of Texas, Austin)

q Fast Predicate-Aware Dataflow Analysis Slides

Kazuaki Ishizaki, Akira Koseki, Hideaki Komatsu, Toshio Nakatani (IBM Reasearch, Tokyo)

q On Speculative Optimizations Using Alias Profiling and Heuristics for C Programs Slides

Jin Lin, Tong Chen, Wei-Chung Hsu, Peng-Chun Yew (Univ of Minnesota)

q Compiler Controlled Register Stack Management for the Intel Itanium Architecture Slides

Alex Settle, Dan Connors (Univ of Colorado, Boulder),

Gerolf Hoflehner, Dan Lavery (Intel Corp)

q Dynamic Profile-Guided Optimizations in Managed Runtimes Slides

Shirish Aundhe, Greg Eastman (Intel Corp)

q Compiler Optimizations for TPC-C Workloads on Linux Slides

Gerolf Hoflehner, Knud Kirkegaad, Dan Lavery, Yong-fong Lee,

Wei Li, Rod Skinner (Intel Corp)

Program Co-chairs

Gerolf Hoflehner (gerolf.f.hoflehner@intel.com)